1. Field of the Invention
Embodiments of the invention relate generally to phase change random access memory (PRAM) devices and related methods of operation. More particularly, embodiments of the invention relate to PRAM devices and related methods of performing program operations including divisional program operations and verify read operations.
2. Description of Related Art
Phase change memory devices store data using phase change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases. The amorphous and crystalline phases (or states) exhibit different resistance values used to distinguish different logic states of memory cells in the memory devices. In particular, the amorphous phase exhibits a relatively high resistance and the crystalline phase exhibits a relatively low resistance.
At least one type of phase change memory device—PRAM—uses the amorphous state to represent a logical ‘1’ and the crystalline state to represent a logical ‘0’. In a PRAM device, the crystalline state is referred to as a “set state” and the amorphous state is referred to as a “reset state”. Accordingly, a memory cell in a PRAM stores a logical ‘0’ by setting a phase change material in the memory cell to the crystalline state, and the memory cell stores a logical ‘1’ by setting the phase change material to the amorphous state. Various PRAM devices are disclosed, for example, in U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase change material in a PRAM is converted to the amorphous state by heating the material to a first temperature above a predetermined melting temperature and then quickly cooling the material. The phase change material is converted to the crystalline state by heating the material at a second temperature lower than the melting temperature but above a crystallizing temperature for a sustained period of time. Accordingly, data is programmed to memory cells in a PRAM by converting the phase change material in memory cells of the PRAM between the amorphous and crystalline states using heating and cooling as described above.
The phase change material in a PRAM typically comprises a compound including germanium (Ge), antimony (Sb), and tellurium (Te), i.e., a “GST” compound. The GST compound is well suited for a PRAM because it can quickly transition between the amorphous and crystalline states by heating and cooling. In addition to, or as an alternative for the GST compound, a variety of other compounds can be used in the phase change material. Examples of the other compounds include, but are not limited to, 2-element compounds such as GaSb, InSb, InSe, Sb2Te3, and GeTe, 3-element compounds such as GeSbTe, GaSeTe, InSbTe, SnSb2Te4, and InSbGe, or 4-element compounds such as AginSbTe, (GeSn)SbTe, GeSb(SeTe), and Te81 Ge15Sb2S2.
The memory cells in a PRAM are called “phase change memory cells”. A phase change memory cell typically comprises a top electrode, a phase change material layer, a bottom electrode contact, a bottom electrode, and an access transistor. A read operation is performed on the phase change memory cell by measuring the resistance of the phase change material layer, and a program operation is performed on the phase change memory cell by heating and cooling the phase change material layer as described above.
Unfortunately, conventional PRAM devices can receive several bits of input at the same time but are unable to simultaneously program the bits into corresponding memory cells. For example, a PRAM may receive 16 inputs through a plurality of pins, but the PRAM may not be able to simultaneously access 16 phase change memory cells. One reason for this shortcoming is that if a current of 1 mA is required to program one phase change memory cell, then a current of 16 mA would be required to simultaneously program 16 phase change memory cells. Moreover, if the efficiency of a driver circuit providing the current is 10%, then in reality, a current of 160 mA would be required to simultaneously program the 16 memory cells. However, conventional PRAM devices are generally not equipped to provide currents with such high magnitudes.
Since a program driver in a PRAM device can only provide a limited amount of current, a program operation of several phase change memory cells can be divided into several “divisional program operations” each requiring only a fraction of the total current required to program all of the several phase change memory cells. In each divisional program operation, a subset (i.e., a “division”) of memory cells among a larger group are programmed. For example, a group of sixteen phase change memory cells can be programmed by dividing the sixteen phase change memory cells into eight groups (i.e., divisions) of two and simultaneously programming the two memory cells in each group of two in eight successive divisional program operations.
To prevent unnecessary current consumption and programming failures, the PRAM device may also perform a verify read operation to verify the program status of each selected memory cell. To perform the verify read operation, program data to be programmed in the selected memory cells is stored in a temporary storage location such as a program buffer. Next, the program data is programmed into selected cells. Then, the data stored in the selected memory cells is read and compared with the program data stored in the temporary storage location. Where the data stored in the temporary storage location is different from the data stored in the selected memory cells, the verify read operation indicates a program failure. Otherwise, the verify read operation indicates a program success.
FIG. 1 is a conceptual timing chart illustrating a conventional method of operating a PRAM device that uses divisional program operations. For explanation purposes, it will be assumed that a program operation of the PRAM device programs 16 bits of data to 16 selected memory cells divided into eight pairs, or groups, using eight divisional program operations.
Referring to FIG. 1, data is programmed in the PRAM device using a plurality of program loops (L=1 through “k”). Before each program loop begins, a verify read operation is performed to detect memory cells, among the selected memory cells, that have not been successfully programmed. Thereafter, a divisional program operation is performed on groups of memory cells where at least one memory cell has not been successfully programmed—referred to as “failed groups” (incidentally, individual memory cells that have not been successfully programmed will be referred to as “failed cells”). In the example of FIG. 1, eight divisional program operations {circumflex over (1)} through {circumflex over (8)} correspond to eight respective cell groups.
In a program operation, all eight groups of memory cells generally begin as failed groups. Accordingly, in the first program loop (L=1), a divisional program operation is typically executed for each of the eight groups. In the second program loop (L=2), assuming that the third and fourth groups have been successfully programmed, a divisional program operation is performed on all eight groups, except for the third and fourth groups. Similarly, in remaining program loops, fewer groups are programmed as more groups become successfully programmed.
Unfortunately, conventional methods such as that illustrated in FIG. 1 may be unnecessarily slow due to time gaps where no programming is performed, such as the time gap between the second and fifth divisional program operations of the second program loop (L=2).